The present invention relate to a semiconductor device, and more particularly, to a method for fabricating an etching barrier by using a shadow effect caused by a protrusion structure vertical to a substrate, and a method for fabricating one side contact of a vertical transistor by using the same.
As the integration density of semiconductor devices has been increased, many efforts have been made to integrate a larger number of unit elements, such as transistors, within a limited area of a substrate. In the case of a memory device such as a DRAM device, attempts have been made to implement a single memory cell in a unit area of 4F2 (where F is a minimum feature size). To this end, a vertical transistor has been proposed. In the vertical transistor, an active area structure protruding vertically from the substrate, e.g., an active pillar, is formed and a channel is formed vertically to the protrusion-shaped active region, instead of integrating a cell transistor on the surface of the substrate.
A vertical transistor may be understood as a structure in which junctions for source and drain are formed at upper and lower portions of a vertical pillar, respectively, and a gate is formed on a sidewall of the pillar. In a case in which a DRAM memory cell includes a vertical transistor and a capacitor, a drain junction may be positioned at a lower portion of the vertical pillar. Accordingly, a bit line electrically coupled to the drain junction may be buried within the substrate. Generally, a minimum distance may be desired between bit lines to reduce parasitic capacitance effects between the bit lines. As the integration density of the semiconductor device has increased, the substrate surface area occupied by the memory cell has been greatly reduced.